I took a quick look at JLCPCB`s design rules. I think it`s well done and very logical. (No, I don`t work for JLCPCB.) Here`s what I do and jlcpcb made my boards without any problems: set the net distance to 0.2mm and ignore the via or pad for tracking. The tasks follow the naming guidelines defined here: support.jlcpcb.com/article/29-suggested-naming-patterns This includes tCream/bCream welding paste layers that can be used for stencil service. Mainly based on the standard eagle design rules, it adds the capabilities of the stated JLCPCB listed here: however, jlcpcb.com/capabilities/Capabilities JLCPCB also has minimum distances for via to via, pad to pad, via to track, pad to track, etc. In any case, these minimum values are more than 0.127 mm – for example, the minimum distance on the track is 0.254 mm. I accept that Kicad is not specific to a particular manufacturer, so I don`t expect the design rules to conform to the JLCPCB rules. The predefined CAM work we`ve provided can handle most common designs, but there are exceptions. In this case, you need to tailor CAM`s work to your needs.
Image-based production works best in simple plates and small quantities. If you set all the free spaces to the maximum, as suggested here, everything is fine. And indeed, if your design allows it, please do it. But for tighter boards, it no longer works. You have to go to the limits, and the processor has to optimize the cards to get the yields. For example, the mask is then optimized to the point where the track connects the pad, or a mold is connected to a pad to optimize weldability. On the question of the spacing or width of the weld mask. These two specifications go against each other. The optimum depends on the manufacturing process. It will produce better quality if you let the processor optimize the spacing to optimize the result. Overspecification increases costs and reduces quality. Of course, this is not done for a single $5 prototype, but for volume.
Have a little respect for a processor. He knows something about plate production. He does it to make a living. Help him do a better job. Simply set values above the JLC minimum. You don`t want to have traces at a minimum unless you really have to. I would suggest that you design in mm and not in inches. This way, you won`t make any conversion mistakes. Different manufacturers have different capabilities, such as minimum trace width or drilling size. To ensure that our design meets these standards, we must perform the EAGLE Design Rule Check (DRC) to verify our design. The different copper spacings on the pads are there to meet the design rules of the welding mask. Theoretically, of course, you`re right that if the solder mask is perfect, the processor doesn`t have to worry about those specific distances.
Artworks designed in another graphics software must be imported, it is better to put them to a separate level. I`m not familiar with JLCPCB`s design minimums, but any minimum to a via or a pad is the measurement on the via or pad from the edge of the ring ring, the edge of the hole or the middle of the hole? By « pad » do you mean the THT pad or the SMT pad or both? (In my first question, I may have mistakenly considered only THT buffers.) This does not mean that the processor needs to know where the vias are. You can just have a tighter tolerance of both for both and that`s it. In fact, jlcpcb publishes hole tolerances as a single common value for all holes. I think they don`t rely on the mask included for a significant part of the work and optimize it according to their needs, hence their interest in the underlying rules on copper. However, I agree with you, saying something that your customers can`t fill out or verify doesn`t make sense. They found other ways to confuse their customers than through hole tolerances! (-: The ULP can extract the LCSC part order numbers from the package attributes. The attribute must be named LCSC_PART or LCSC and must contain the command code found in the jlcpcb.com/client/index.html#/parts parts library (for example, C25804). The top and/or bottom assembly can be selected directly during the ordering process, JLCPCB uses the CPL file to determine which side the identifier was placed on. JLC has listed its capabilities on its website here: jlcpcb.com/capabilities/Capabilities JLCPCB is a popular new source for ordering printed circuit boards. Their advertised price for printed circuit boards is extremely low, although shipping costs are usually $20 to $30. Nevertheless, it`s usually cheaper than sources like OSH Park, especially when ordering in bulk.
Their construction times are also very fast, so the result is cheaper, faster PCB of comparable quality. The only downside is that their website isn`t as user-friendly and sometimes outdated. Therefore, I am writing this article to show you how to export your EAGLE design to files that JLCPCB accepts and that you get without manufacturing defects. Once you`ve completed your design in Eagle, the last step before sending it to the Fab House is to generate the Gerber and Drill files. PCB fab houses use these gerber and drill files to make your cards. Autodesk EAGLE includes a handy computer-aided manufacturing (CAM) processor that allows you to load a CAM file and quickly generate the specific files you need for your design. This seems like a good thread to continue a discussion about the JLCPCB rules. In the configuration of the Kicad board, Net Classes, I can define a « clearance », but it is not clear what the clearance value refers to in relation to the total set of minimum clearances that JLC gives.
I used the gauge kindly provided by Seth_h, which has a distance of 0.127 mm and this corresponds to the minimum distance of JLC for rails – it must be at least 0.127 mm between the nearest rail edges. It also has a hole-to-hole minimum of 0.25mm, although the minimum JLCPCB is 0.5mm (which is easy to fix). Hello. I apologize for starting a topic about it, but I`m inexperienced in PCB design. So I check my network classes to comply with JLCPCB design rules, but I have some doubts. I always use the OSH Park Gerber Previewer in combination with the JLCPCB one to make sure things will be as I expect, I have a design template for JLCPCB in github.com/sethhillbrand/kicad_templates that uses their rules for KiCad DRC. You can find a useful starting point Open jlcpcb.com/ and click on one of the « QUOTE NOW » buttons.